GDL

Journal from gdlhub / 2020-12-04 10:20:07
By : Shaveta Thakral, Dipali Bansal, Telkomnika
Created : 2020-12-04, with 1 files

Keyword : ALU; fault tolerant; power dissipation; reversible logic; synthesis;
Url : http://journal.uad.ac.id/index.php/TELKOMNIKA/article/view/12645
Document Source : WEB

Miniaturization, cost, functionality, complexity and power dissipation are important and necessary design traits which need attention in circuit designing. There is a trade off between miniaturization and power dissipation. Smart technology is always searching for new paradigms to continue improve power dissipation. Reversible logic is one of smart computing deployed to avoid power dissipation. Researchers have proposed many reversible logic-based arithmetic and logic units (ALU). However, the research in the area of fault tolerant ALU is still under progress. The aim of this paper is to bridge the knowledge gap for a new researcher in area of fault tolerance using parity preserving logic gates rather than searching huge data through various sources. This paper also presents a high functionality based novel fault tolerant arithmetic and logic unit architecture. A comparison on optimization aspects is presented in tabular form and results shows that proposed ALU architecture is optimum balance in terms of all aspects of reversible logic synthesis. The proposed ALU architecture is coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool. The quantum cost of all gates used in proposed architecture is verified using RCViewer + tool.

Give Comment ?#(0) | Bookmark

Property	Value
Publisher ID	gdlhub
Organization	Telkomnika
Contact Name	Herti Yani, S.Kom
Address	Jln. Jenderal Sudirman
City	Jambi
Region	Jambi
Country	Indonesia
Phone	0741-35095
Fax	0741-35093
Administrator E-mail	elibrarystikom@gmail.com
CKO E-mail	elibrarystikom@gmail.com