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Study and Design of 40 nW CMOS Temperature Sensor for Space Applications

Journal from gdlhub / 2016-11-16 03:17:24
By : Abhishek Pandey, Vijay Nath, Telkomnika
Created : 2015-09-01, with 1 files

Keyword : CMOS; complementary metal oxide semiconductor; VLSI; very large scale integration circuit; SOI: system on insulator; PTAT: proportional to absolute temperature; NTC: negative temperature coefficient, SoC: system on chip.
Url : http://journal.uad.ac.id/index.php/TELKOMNIKA/article/view/1426

In this paper, a novel CMOS temperature sensors based on sub-threshold MOS operation has been presented, which is designed for space and satellite applications. This proposed CMOS temperature sensor is enunciated good linearity between temperatures range from -55OC to 150OC with inaccuracy of 0.85 OC/V. This circuit is operated at supply 1V and static power consumption 40nW is achieved. The proposed circuit is based on the MOS threshold voltage and mobility. There are two type of sensor output in presented circuit first, voltage proportional to absolute temperature (PTAT) due to threshold voltage and second, negative temperature coefficient (NTC) due to mobility. This circuit is designed & simulated using Cadence analog & digital system design tools UMC90nm CMOS technology. The layout area of the circuit is 17.213μm 6.655μm. This is a low power and longer battery life for harsh environment, wireless sensor network applications etc

Description Alternative :

In this paper, a novel CMOS temperature sensors based on sub-threshold MOS operation has been presented, which is designed for space and satellite applications. This proposed CMOS temperature sensor is enunciated good linearity between temperatures range from -55OC to 150OC with inaccuracy of 0.85 OC/V. This circuit is operated at supply 1V and static power consumption 40nW is achieved. The proposed circuit is based on the MOS threshold voltage and mobility. There are two type of sensor output in presented circuit first, voltage proportional to absolute temperature (PTAT) due to threshold voltage and second, negative temperature coefficient (NTC) due to mobility. This circuit is designed & simulated using Cadence analog & digital system design tools UMC90nm CMOS technology. The layout area of the circuit is 17.213μm 6.655μm. This is a low power and longer battery life for harsh environment, wireless sensor network applications etc

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