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Energy, Throughput and Area Evaluation of Regular and Irregular Network on Chip Architectures

Energy, Throughput and Area Evaluation of Regular and Irregular Network on Chip Architectures

ISSN : 0976 - 9757
Journal from gdlhub / 2017-08-14 11:52:33
Oleh : Umamaheswari S1, Rajapaul Perinbam J2, International Journal of Distributed and Parallel systems
Dibuat : 2012-06-26, dengan 1 file

Keyword : Network on Chip (NoC), Irregular topology, performance comparison, Topology generation, Throughput, Energy, silicon area.
Subjek : Energy, Throughput and Area Evaluation of Regular and Irregular Network on Chip Architectures
Url : http://airccse.org/journal/ijdps/papers/0911ijdps04.pdf
Sumber pengambilan dokumen : Internet

Network-on-chip has been proposed in System-on-Chip to achieve high performance, reusability and


scalability through generating application specific topologies. Application specific topologies are


irregular in structure and take into account certain factors like communication weight, area and energy


constraints while building up the topology. Regular topologies like 2D mesh, spidergon are more


structured and are built not considering much about the system characteristics and other requirements.


Consequently the throughput, power utilization and silicon area vary depending on the topology. This


paper provides an evaluation of the performance measures of the regular topological structures and


irregular application specific NoC.

Deskripsi Alternatif :

Network-on-chip has been proposed in System-on-Chip to achieve high performance, reusability and


scalability through generating application specific topologies. Application specific topologies are


irregular in structure and take into account certain factors like communication weight, area and energy


constraints while building up the topology. Regular topologies like 2D mesh, spidergon are more


structured and are built not considering much about the system characteristics and other requirements.


Consequently the throughput, power utilization and silicon area vary depending on the topology. This


paper provides an evaluation of the performance measures of the regular topological structures and


irregular application specific NoC.

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OrganisasiInternational Journal of Distributed and Parallel systems
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