GDL

Hardware Implementation Low Power High Speed FFT Core

2008
Journal from gdlhub / 2017-08-14 11:52:32
Oleh : Muniandi Kannan, Srinivasa Srivatsa, IAJIT
Dibuat : 2012-06-23, dengan 1 file

Keyword : Pipelined architecture, shift register, finite state machine, common sub-expression, multiplier-less architecture.
Subjek : Hardware Implementation Low Power High Speed FFT Core
Url : http:// Pipelined architecture, shift register, finite state machine, common sub-expression, multiplier-less architecture.
Sumber pengambilan dokumen : Internet

In recent times, DSP algorithms have received increased attention due to rapid advancements in multimedia


computing and high-speed wired and wireless communications. In response to these advances, the search for novel


implementations of arithmetic-intensive circuitry has intensified. For the portability requirement in telecommunication


systems, there is a need for low power hardware implementation of fast fourier transforms algorithm. This paper proposes the


hardware implementation of low power multiplier-less radix-4 single–path delay commutator pipelined fast fourier transform


processor architecture of sizes 16, 64 and 256 points. The multiplier-less architecture uses common sub-expression sharing to


replace complex multiplications with simpler shift and add operations. By combining a new commutator architecture and low


power butterfly architecture with this approach power reduction is achieved. When compared with a conventional fast fourier


transform architecture based on non-booth coded wallace tree multiplier the power reduction in this implementation is 44%


and 60% for 64-point and 16-point radix-4 fast fourier transforms respectively. The power dissipation is estimated using


cadence RTL compiler. The operating frequencies are 166 MHz and 200 MHz, for 64 point and 16 point fast fourier


transforms, respectively. Our implementation of the 256 point FFT architecture consumes 153 mw for an operating speed of


125 MHz

Deskripsi Alternatif :

In recent times, DSP algorithms have received increased attention due to rapid advancements in multimedia


computing and high-speed wired and wireless communications. In response to these advances, the search for novel


implementations of arithmetic-intensive circuitry has intensified. For the portability requirement in telecommunication


systems, there is a need for low power hardware implementation of fast fourier transforms algorithm. This paper proposes the


hardware implementation of low power multiplier-less radix-4 single–path delay commutator pipelined fast fourier transform


processor architecture of sizes 16, 64 and 256 points. The multiplier-less architecture uses common sub-expression sharing to


replace complex multiplications with simpler shift and add operations. By combining a new commutator architecture and low


power butterfly architecture with this approach power reduction is achieved. When compared with a conventional fast fourier


transform architecture based on non-booth coded wallace tree multiplier the power reduction in this implementation is 44%


and 60% for 64-point and 16-point radix-4 fast fourier transforms respectively. The power dissipation is estimated using


cadence RTL compiler. The operating frequencies are 166 MHz and 200 MHz, for 64 point and 16 point fast fourier


transforms, respectively. Our implementation of the 256 point FFT architecture consumes 153 mw for an operating speed of


125 MHz

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