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Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog

ISSN : 0976 - 1357
Journal from gdlhub / 2017-08-14 11:52:34
Oleh : Addanki Purna Ramesh1, A.V. N. Tilak2 and A.M.Prasad3, International journal of VLSI design & Communication Systems
Dibuat : 2012-07-04, dengan 1 file

Keyword : Radix -2 modified booth algorithm, Digital signal processing, spurious power suppression Technique, Verilog.
Subjek : Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog
Url : http://airccse.org/journal/vlsi/papers/3312vlsics10.pdf
Sumber pengambilan dokumen : Internet

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high


speed arithmetic. High speed and low power MAC units are required for applications of digital signal


processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving


the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and


spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the


unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic


power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of


bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm


MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

Deskripsi Alternatif :

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high


speed arithmetic. High speed and low power MAC units are required for applications of digital signal


processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving


the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and


spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the


unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic


power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of


bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm


MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

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